In recent years, in order to further increase the speed and the capacity of an optical communication system, the adoption of a multilevel modulation method (Quadrature Amplitude Modulation (QAM)) or the like is being considered. A transmission device of such an optical communication system requires a high-speed digital-to-analog converter (to be referred to as a DAC hereinafter) to generate a multilevel modulation signal. To implement a high-speed DAC, a time-interleaved device as that shown in FIG. 19 is effective (for example, see Non-Patent Literature 1). The time-interleaved digital-to-analog conversion device shown in FIG. 19 will be described here.
A first digital-to-analog converter DAC1 performs analog/digital conversion and outputs a first analog signal A1 when an N-bit first digital signal D1 is input to an input terminal and a clock signal CLK (0°) that has been phase-shifted by 0° by a phase shifter S1 is input to a sync input terminal. A second digital-to-analog converter DAC2 performs analog/digital conversion and outputs a second analog signal A2 when an N-bit second digital signal D2 is input to an input terminal and the clock signal CLK (180°), which has been phase-shifted by 180° by a phase shifter S2, is input to a sync input terminal. Upon input of the first and second analog signals A1 and A2 and the clock signal CLK (90°) that has been phase-shifted by 90° by a phase shifter S3, an analog multiplexer core circuit M performs a time-multiplexing process and outputs a time-multiplexed analog signal Aout.
Note that FIG. 20 is a timing chart showing the signal waveforms of the digital-to-analog conversion device of FIG. 19. (a) indicates the analog signal A1, (b) indicates the analog signal A2, (c) indicates the time-multiplexed analog signal Aout, (d) indicates the clock signal CLK (0°) to be input to the digital-to-analog converter DAC1, (e) indicates the clock signal CLK (180°) to be input to the digital-to-analog converter DAC2, and (f) indicates the clock signal CLK (90°) to be input to the analog multiplexer core circuit M.
In the time-interleaved digital-to-analog conversion device shown in FIG. 19, the performance of the analog multiplexer core circuit M, which serves as a component, has a large influence on the characteristics of the entire device.
The analog multiplexer can be regarded as an analog switch functionally, as shown in FIG. 21. That is, when the switching cycle is set as 1/fSW by setting the switching frequency as fSW, the analog multiplexer has a function of outputting the time-multiplexed analog signal Aout by switching between an analog signal Ain1 and an analog signal Ain2 as input signals and selectively outputting one of the signals.
An example of a general analog-multiplexer core circuit with the simplest arrangement is shown in FIG. 22. In this circuit, analog signals can be selectively switched and output by FET gating. That is, in this analog multiplexer core circuit, the drain of FET gating F1 is connected to the drain of FET gating F2, and the connecting portion serves as an output terminal. In the FET gating F1, the analog signal Ain1 is input to the source and a positive-phase signal CLK+ is input to the gate. In the FET gating F2, the analog signal Ain2 is input to the source and a negative-phase signal CLK− (which is phase-shifted by 180° with respect to the positive phase) is input to the gate. This sets the FET gating F1 and FET gating F2 to be alternately in a conductive state and causes the time-multiplexed analog signal Aout to be output.
The analog multiplexer core circuit shown in FIG. 22 has good linearity but has problems with high-speed operation. This is because the switching speed between the FET gating F1 and the FET gating F2 cannot reach the required high speed.
On the other hand, in the case of a multiplexer (core) circuit that handles digital signals as shown in FIG. 23, there have been many reports of circuits that operate at a speed of 50 Gb/s or more (for example, see Non-Patent Literature 2). The multiplexer core circuit shown in FIG. 23 is formed using emitter-coupled logic (ELC) and is capable of extremely high-speed operation by causing a transistor to operate in a non-saturation region. A detailed description of this circuit will be given hereinafter. Note that in the following description, a negative-phase signal of a given signal, with respect to a positive-phase signal of the given signal, indicates a signal which has the same amplitude but has a phase which has been inverted by 180°.
A differential pair 11 arranged on an upper stage of the circuit diagram is formed by emitter-coupled logic in which the emitter of a transistor Q1 is connected to the emitter of a transistor Q2. Each of the collectors of the transistors Q1 and Q2 is connected to a high-potential power supply VCC via a corresponding one of collector resistors Rc1 and Rc2. A positive-phase signal Din1+ of a first digital signal is input to the base of the transistor Q1. A negative-phase signal Din1− of the first digital signal is input to the base of the transistor Q2.
A differential pair 12 arranged on an upper stage of the circuit diagram is formed by emitter-coupled logic in which the emitter of a transistor Q3 is connected to the emitter of a transistor Q4. Each of the collectors of the transistors Q3 and Q4 is connected to the high-potential power supply VCC via a corresponding one of the collector resistors Rc1 and Rc2. A positive-phase signal Din2+ of a second digital signal is input to the base of the transistor Q3. A negative-phase signal Din2− of the second digital signal is input to the base of the transistor Q4.
An output terminal OUT+ is connected to the collectors of the respective transistors Q2 and Q4. An output terminal OUT− is connected to the collectors of the respective transistors Q1 and Q3.
A differential pair 13 arranged on the lower stage in the circuit diagram is formed by emitter-coupled logic in which the emitter of a transistor (fifth transistor) Q5 is connected to the emitter of a transistor (sixth transistor) Q6. The collector of the transistor Q5 is connected to the emitters of the respective transistors Q1 and Q2. The collector of the transistor Q6 is connected to the emitters of the respective transistors Q3 and Q4. A positive-phase signal CLK+ of a clock signal CLK is input to the base of the transistor Q5. A negative-phase signal CLK− of the clock signal CLK is input to the base of the transistor Q6.
One terminal of a constant current source 14 is connected to the emitters of the respective transistors Q5 and Q6. The other terminal of the constant current source 14 is connected to a low-voltage power supply VEE. The constant current source 14 causes a constant current IEE of a predetermined constant value to flow.
In the multiplexer core circuit shown in FIG. 23, the transistor Q5 is set to a conductive state and the transistor Q6 is set to a cut-off state when the positive-phase signal CLK+ of the clock signal CLK is at high level (H) and the negative-phase signal CLK− is at low level (L). Hence, the first digital signals Din1+ and Din1− are amplified by the first differential pair 11 (transistors Q1 and Q2) and output from the output terminals OUT+ and OUT−. On the other hand, when the positive-phase signal CLK+ of the clock signal is at L and the negative-phase signal CLK− of the clock signal is at H, the transistor Q6 is set to the conductive state and the transistor Q5 is set to the cut-off state. Hence, the second digital signals Din2+ and Din2− are amplified by the second differential pair 12 (transistors Q3 and Q4) and output from the output terminals OUT+ and OUT−.
In this manner, in accordance with the signal levels of the clock signals CLK+ and CLK− alternately changing between H and L, the first digital signals Din1+ and Din1− and the second digital signals Din2+ and Din2− are alternately output as time-multiplexed digital signals Dout+ and Dout− from the output terminals OUT+ and OUT−.
However, in the circuit arrangement shown in FIG. 23, it is difficult to handle an analog signal since waveform distortion is generated because linearity of response to an input signal cannot be ensured. This is because when the amplitude of the input signal is too large, the amplification of the differential pairs 11 and 12 is restricted and the amplitude of the output signal is restricted. As a result, the output signal is distorted when an analog signal is handled.